15th International Test Synthesis Workshop

ITSW 2008

April 7-9, 2008

University of California

Santa Barbara, California, USA

General Chair

N. Mukherjee – Mentor G.

Past General Chair

S. Patil – Intel

Vice Chair

J. Dworak – Brown U.

Program Co-Chairs

N. Touba – U. Texas, Austin

S. Chakravarty - LSI

Panels Chair

V. Chickermane – Cadence

Publicity Chair

A. Jas – Intel

Finance Chair

C. Barnhart – Silicon Aid

Local Arrangements Chair

L. C. Wang – UC SB

European Liaison

M. Zwolinski – U. Southampton

Asian Liaison

C. W. Wu – Nat. Tsing Hua U.

Program Committee

M. Abadir – FreeScale

R. Aitken – ARM

K. Balakrishnan – AMD

S. Blanton – Carnegie Mellon U.

D. Burek – Magma

K. Chakrabarty – Duke U.

K.-T.Cheng – UC SB

A. Crouch – Inovys

R. Datta – TI

S. Davidson – Sun Micro.

C. Dixit – LSI

D. Goswami – Mentor Graphics

A. Guettaf – Broadcom

M. Hsiao – Virginia Tech.

K. Iwasaki – Tokyo Metro. U.

R. Kapur – Synopsys

M. Laisne – QualComm

K.-J. Lee – Nat. Cheng-Kung U.

A. Majumdar – Sun Micro.

S. Mitra - Stanford

K. Mohanram - Rice U. Texas

M. Nourani –U. Texas, Dallas

A. Orailoglu – UC San Diego

B. Pouya – Freescale

J. Qian – Cisco

J. Rajski – Mentor Graphics

S. M. Reddy – U. Iowa

M. Tahoori – Northeastern U.

S. Tragoudas – S. Illinois U.

H. Walker – Texas A&M U.

Call For Papers Theme: At-Speed Scan: Challenges and Opportunities Since the inception of ITSW in Santa Barbara in 1994 chip geometries have shrunk from 500 to 65 nanometers with 45 nanometers on the near horizon. Digital circuit speeds have moved from the 100-200 MHz range to 2-3 GHz and higher. This amazing shrinkage and speedup has been spurred by innovative algorithms, tools and methodologies in all aspects of digital chip design and manufacturing. The widespread use of all aspects of Test Synthesis coupled with powerful pre-silicon verification approaches has been able to keep up with increasing chip complexity. This year’s workshop will focus on at-speed scan tests, looking at various issues like hardware support, yield loss, test power, defect coverage and pseudo-functional tests. Is it possible to replace functional delay tests with at-speed scan and still maintain product quality? As always ITSW will also consider the usual papers in the area of Test Synthesis including, but not limited, to the following:

Register Transfer Level DFT High-Level/Behavioral Test Synthesis System-on-a-Chip (SOC) DFT Memory and Logic BIST Test Synthesis for Debug and Diagnosis DFT for Mixed-Signal Circuits Test Resource Partitioning Functional Verification

Power and Noise-Aware Test Design for Reliability High-speed I/O test Reducing the Cost of Test Design for Manufacturing and Yield Board and System Test SER / Concurrent error detection Test Synthesis for Reconfigurable Logic

For more information, please refer to the web site: http://www.tttc-itsw.org.

To present recent research results at the workshop, please submit an extended abstract, one to three pages long, in PDF format by January 9, 2008. Acceptance notifications will be sent out on February 27, 2008. Please include the names, affiliations, and full contact information of all authors. Also, indicate which author will be the speaker if the abstract is accepted for presentation. To support open discussion, no proceedings of the workshop will be published. As in previous years, ITSW will present a BEST Student Paper Award to encourage student participation in the workshop.

For general information, contact:

Nilanjan Mukherjee, General Chair

Mentor Graphics Corporation

Wilsonville, OR 97070

Phone: 503.685.1721,

FAX: 503.685.4729

Submit extended abstracts via email to:

Nur Touba

Electrical and Computer Engineering

University of Texas, Austin, TX

Phone: 512.232.1456

FAX: 512.471.5532