ITSW 2005 Final Program
 

April 11, 2005 (Monday)
 
7:00 - 8:00 AM   CONTINENTAL BREAKFAST:  MEETING ROOM FOYER    
 
8:00 - 10:00 AM   Test Time and Test Data Volume Reduction Techniques   Chair: Carl Barnhart (Cadence)
  8:00 - 8:30   Test Time Reduction using Dual Scan Chain design   Sandeep Bhatia (Cadence)
  8:30 - 9:00   Analysis of Test Coverage in Illinois Scan Based Compression Technology through Real Implementations   Anis Uzzaman, Brion Keller, Vivek Chickermane (Cadence)
  9:00 - 9:30   Test Data Compression for IP Cores Using Selective Encoding of Scan Slices   Zhanglei Wang and Krishnendu Chakrabarty (Duke U.)
  9:30 - 10:00   Reduce Testing Time by Partitioning the Scan Flops and Pipelining Excitation and Propagation of Different Fault Sets   Xiaoding Chen and Michael S. Hsiao (Virginia Tech).
 
10:00 - 10:30 AM COFFEE BREAK    
           
10:30 - 12:00 PM   Delay Test   Chair: Sudhakar Reddy (U. Iowa)
  10:30 - 11:00   Metrics for Selection of High Quality Delay Tests   Hangkyu Lee, Suriya Natarajan, Srinivas Patil and Irith Pomeranz (Purdue, Intel).
  11:00 - 11:30   The Delay Evaluation Methodology by Using Low-Voltage Wireless-Tester   Ching-Hwa Cheng (Feng-Chia U., Taiwan)
  11:30 - 12:00   Methods to Increase Transition Fault Coverage of Broadside Tests    N. Devtaprasanna, A. Gunda, S.M. Reddy and I. Pomeranz.
           
12:00 - 1:30 PM    LUNCH    
           
1:30 - 3:30 PM   Logic BIST   Chair:  Abhijit Jas (Intel)
  1:30 - 2:00   SLING: A Procedure for Synthesis of Linear Test Pattern Generators with Strong Randomness Properties   Avijit Dutta and Nur A. Touba (UT Austin).
  2:00- - 2:30   Low Overhead BIST using Complementary Weight Patterns   Liyang Lai, Janak H. Patel, Thomas Rinderknecht and Wu-Tung Cheng.
  2:30 - 3:00   Low Power BIST Based on Scan Chain Partitioning   Jinkyu Lee and Nur A. Touba (UT Austin).
  3:00 - 3:30   Logic BIST Diagnostics Using Simple Synchronised MISR Unload   Chris Hill and Thomas Rinderknecht.
 
3:30 - 4:00 PM   COFFEE BREAK    
           
4:00 - 5:30 PM   High-Level TEST   Chair: Mark Zwolinski (U. Southampton)
  4:00 - 4:30   Constraint-Based Test Generation for Behavioral VHDL Descriptions   F. Xin, M. Ciesielski and I. G. Harris.
  4:30 - 5:00   A System for Automatic Insertion of 1149.6 Compliant Boundary Scan   Brian Foutz, Vivek Chickermane, Harry Linzer, Bing Li and Patrick Brown (Cadence)
  5:00 - 5:30   DFT Signoff at RTL using Predictive Technique   Douglas Kay, Young Lee, Sung Chung (Cisco) and Ralph Marlett (Atrenta).
           
DINNER (On Your Own)
           

April 12, 2005 (Tuesday)
           
7:00 - 8:00 AM   CONTINENTAL BREAKFAST: MEETING ROOM FOYER    
           
8:00 - 10:00 AM   Diagnosing Failures   Chair: Srikanth Venkataraman (Intel)
  8:00 - 8:30   Automatically Linking Logical Tester Failures to Physical Defect Locations   Jay Jahangiri & Nilanjan Mukherjee (Mentor)
  8:30 - 9:00   Novel Techniques for IP-Secure ATPG Diagnostics   Michael Laisne and Hailong Cui (Qualcomm)
  9:00 - 9:30   Debugging and Diagnosing Scan Chains   Alfred L. Crouch (Innovys)
  9:30 - 10:00   A Preliminary Look at Utilizing Excitation Balance and Mandatory Assignment Identification for Defect Diagnosis   Jennifer Dworak (Brown U.).
           
10:00 - 10:30 AM   COFFEE BREAK    
           
10:30 - 12:00 PM   EMBEDDED TUTORIAL - Coping with Soft Errors   Chair: Tim Cheng (UC Santa Barbara)
  10:30 - 11:15   Presenter: Sung. S. Chung (Cisco Systems)    
  11:15 - 12:00   Presenter: T. M. Mak (Intel Corporation)    
           
12:00 - 2:00 PM   LUNCH ON THE BEACH (OPPOSITE DOUBLETREE HOTEL)