ITSW 2004 FINAL PROGRAM

Monday

8:00AM - Novel Test Generation Techniques, Session Chair: Michael Laisne - Qualcomm

Dhiraj Pradhan - University of Bristol, "A New Test Generator with Improved Fault Coverage".
Xinli Gu, Cyndee Wang, Abby Lee and Bill Eklow - Cisco Systems Inc., "Improving Tester Memory Usage by Incremental ATPG and Coverage Gradient Analysis".
Brad Cobb, James Wingfield and M. Ray Mercer - Texas A&M, "Binary Decision Diagrams and Their Applications in Manufacture Testing".
Bruce Jilek, Abhijit Jas, Dinos Moundanos, Michael Mateja and Madhukar Reddy - Intel, "Partitioned ATPG: A Strategy for High-Capacity and High-Performance ATPG for Large Designs".

10:00AM - Session: BIST Reseeding and Compression, Session Chair: Ian G. Harris - University of California Irvine

Antony V. Hirudayaraj, Subhasish Mitra and Kee Sup Kim - Intel, "X-Compact and Xpand on Intel Designs: Key Learnings".
Jiann-Chyi Rau, Ta-Wei Yang and Ying-Fu Ho - Tamkang University, "An Efficient Reseeding With Modifying Technique for Pseudo-Random-Based BIST".
Jinkyu Lee and Nur Touba - University of Texas Austin, "Low Power LFSR Reseeding".

11:30PM - Session: Reconfigurable Architectures, Session Chair: Al Crouch - Inovys

Mehdi Tahoori - Northeastern University, and Subhashish Mitra - Intel, "Thorough Delay Testing of Designs on Programmable Logic Devices".
Jason G. Brown and Shawn Blanton - Carnegie Mellon University, "CAEN-BIST: Testing the NanoFabric".

12:20 - LUNCH

2:00PM - Session: Scan Techniques and Architectures, Session Chair: Carl Barnhart - Cadence Design Systems

John C. Potter, Al Crouch - Inovys, "Scan Techniques for Debug and Diagnosis".
Nodari Sitchinava - Synopsys, Samitha Samaranayake - Oracle, Rohit Kapur- Synopsys, Emil Gizdarski - Synopsys, Fredric Neuveux - Synopsys, and T. W. Williams - Synopsys, "Dynamically Reconfigurable Shared Scan-in Architecture".
Jiann-Chyi Rau, Ching-Hsiu Lin, and Jun-Yi Chang - Tamkang University, "The Optimal Layout-Based Multi-Scan-Chain Scheme".

3:35PM - Session: Defect-Based/Parametric Test, Session Chair: Li C. Wang - University of California Santa Barbara

Jennifer Dworak and M. Ray Mercer - Texas A&M, "Defect Detectability Classes and their Effect on Optimal Test Pattern Generation Strategies".
Bor-Song Liu, Chung Len Lee, Katherine Shu-Min Li - National Chiao Tung University, and Jwu E Chen - Chung-Hua University, "Crosstalk Fault Testing for SOC Interconnection Lines by Using Oscillation Ring Testing Methodology"
Jwu E Chen and Chung-Huang Yeh - Chung-Hua University, "Test Guardbanding for Yield and Quality Estimation".

5:10PM - Session: Delay Test, Session Chair: Shawn Blanton - Carnegie Mellon University

Puneet Gupta and Michael Hsiao - Virginia Tech., "ALAPT: A New Transition Fault Model for Small Delay Faults".
Kai Yang, Li-C. Wang and Kwang-Ting Cheng - University of California Santa Barbara, "On the Development of a Statistical Timing Simulator for Timing Validation and Delay Fault Testing".

Tuesday

8:00AM - Session: Test Data Compression Techniques, Session Chair: Hussain Al-Asaad - Uniersity of California Davis

Michael Knieser, David McIntyre, Dan Weyer, Francis Wolff and Chris Papachristou - Case Western Reserve University, "Using LZW Architectures for High Ratio Test Compression".
Kedarnath Balakrishnan and Nur Touba - University of Texas Austin, "Entropy Limits on Test Data Compression".
S. Rajaram, R. Karthik, S. Dhinesh Joseph and V. Abhaikumar - Thiagarajar College of Engineering, "A New Approach to Test Data Compression for BIST".

9:35AM - Embedded Tutorial: "Challenges of Nanometer Technologies", Session Chair: Douglas Kay - Cisco Systems

Al Crouch - Inovys, "Debug Drivers in Nanometer Technologies"
Sandip Kundu - Intel, "Testing for Circuit Marginalities"
Manuel D'Abreau and Amit Majumdar - Sun Microsystems, "Emerging Test Challenges"

11:50AM - LUNCH / SOCIAL EVENT
An amphibious tour of beautiful Santa Barbara and the waters offshore, followed by a "Cowboy Luau" on the beach opposite the Fess Parker Inn.

3:00PM Panel: New Defects for a New Millennium, Session Chair: Vivek Chickermane - Cadence Design Systems

As device geometries shrink past 130nm, manufacturers are seeing more test escapes from their structural (ATPG and BIST) patterns. This panel will focus on issues regarding the changing nature of defects and the ability or inability of contemporary automatically generated test patterns to detect them. We will hear about problems, successes and, plans to address these issues.
Panelists: TBA

5:00PM - Session: On-chip Compression, Session Chair: Mehdi Tahoori - Northeastern University

Douglas Kay - Cisco Systems, "iBIST (Interactive BIST) application to embedded cores with partial scan implementation".
Vivek Chickermane, Brian Foutz, Brion Keller - Cadence Design Systems, "Synthesis of X-Masking Logic to Support On-Chip Test Compression"

6:00PM Dinner

Wednesday

8:00AM - Session: High-Level Test Synthesis, Session Chair: Nur Touba - University of Texas Austin

M. Zwolinski, M. S. Gaur and P. Oikonomakos - University of Southampton, "Self Testability of Controller/Datapath using a Unified Estimation Technique".
Kiran Ramineni, Shireesh Verma and Ian Harris - University of California Irvine, "A Behavioral Fault Model for the Detection of Design Errors".

9:10AM - Session: Test of Core-Based SoCs, Session Chair: Mark Zwolinski - University of Southampton

Kuo-Liang Cheng, Jing-Reng Huang, Chih-Wea Wang, Chih-Yen Lo, Chih-Tsun Huang, Cheng-Wen Wu - National Tsing Hua University, Shin-Wei Hung and Jye-Yuan Lee - Global UniChip Corp., "Practical Issues and Solutions for SOC Test Integration".
Jiann-Chyi Rau, Wang-Tiao Huang, and Chih-Lung Chien - Tamkang University, "The TAM Architecture for Optimal Testing Scheduling of SOC".

10:20AM - System Test and Analysis, Session Chair: Ian G. Harris - University of California Irvine

Nikhil Dakwala - Stridge Inc., "(E)VCD, STIL Data Transfer Link between Design and ATE".
Sung Chung, Sang Baeg and Hongshin Jun - Cisco Systems, "Programmable Test Pattern and Capture Mechanism for High Speed AC Boundary-Scan".
John C. Potter and Al Crouch - Inovys, "Continuing Story of STIL Love".
Dongwoo Hong, Chee-Kian Ong, Kwang-Ting Cheng and Li-C Wang - University of California Santa Barbara, "Bit Error Rate Estimation for Multi-gigahertz Signals".