ITSW 2008 Presentations
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8:15 - 9:15 AM |
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Opening Session |
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8:15 – 8:30 |
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Opening Message |
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Nilanjan Mukherjee, General Chair |
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Keynote Address |
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8:30 – 9:15 |
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Ken Butler (TI) |
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9:15 - 10:15 AM |
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Test Optimization |
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Chair: X. Lin (Mentor Graphics) |
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9:15 – 9:45 |
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S. Gurumurthy, S. Sambamurthy, J. Abraham (UT-Austin) |
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9:45 – 10:15 |
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Efficient Production Test Selection and Ordering based on Functional Fault Grading |
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J.H. Jeong, D. Mahon, M. Laisne (Qualcomm), A. Ambler (UT-Austin) |
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10:45-12:15 PM |
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DFT |
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Chair: C. Dixit (LSI) |
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10:45 - 11:15 |
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Strategies for Power-Aware DFT |
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V. Chickermane, P. Gallagher, K. Chakravadhanula (Cadence) |
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11:15 - 11:45 |
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Clock Gating to Improve At-Speed Scan |
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D. Dehnert (Intel) |
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11:45 - 12:15 |
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A. Crouch (Asset-Intertech), J. Rearick, K. Posse (AMD) |
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1:30 - 3:30 PM |
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Test Generation and Diagnosis |
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Chair: A. Crouch (Asset-Intertech) |
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1:30 - 2:00 |
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On Tests to Detect Interconnect Opens in Digital CMOS Circuits |
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S. Reddy (U. Iowa), I. Pomeranz (Purdue), C. Liu, and J. Howard (U. Iowa) |
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2:00- - 2:30 |
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Test Generation for Interconnect Opens |
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X. Lin, J. Rajski (Mentor Graphics) |
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2:30 - 3:00 |
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Using Design Validation Input Sequences to Determine Fault Criticality for Test Set Optimization |
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Y. Shi, K. DiPalma, W.-C. Hu, J. Dworak (Brown) |
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3:00 - 3:30 |
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Diagnosis of Design Related Issues with Feature Encoding and Ranking |
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P. Bastani, N. Callegari, L. Wang (UCSB) |
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4:00 – 6:00 PM |
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Test Using Wireless Communication |
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Chair: C.-W. Wu (NTHU) |
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4:00 - 4:30 |
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Wireless Testing of RAM Chips by HOY: Methodology, Architecture, and Prototype Implementation |
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T.-Y. Chang, C.-T. Huang, J.-J. Liou, C.-W. Wu, H.-P. Ma, C.-C. Tien, C.-H. Wang, C.-U. Yang |
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4:30 - 5:00 |
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Wireless Communications Interface Design for HOY Wireless Testing Scheme |
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M.-Y. Chu, T.-Y. Chang, H.-J. Hsu, C.-Y. Lee, C.-F. Li, H.-P. Ma, C.-T. Huang, P.-C. Huang |
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5:00 - 5:30 |
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Improving the Efficiency of Scan Test on Wireless HOY Test Platform |
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C.-W. Tzeng, C.-Y. Lin, S.-Y. Huang, C.-T. Huang, J.-J. Liou, H.-P. Ma, C.-W. Wu |
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5:30 - 6:00 |
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Automatic Wrapper Synthesis and Test Program Generation for Packet-based ATE Platforms |
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Y.-Y. Chen, C.-U. Yang, S.-Y. Chen, J.-J. Liou |
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April 8, 2008 (Tuesday) |
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8:30 - 10:30 AM |
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Scan and BIST |
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Chair: H. Walker (Texas A&M) |
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8:30 - 9:00 |
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Scan-Chain Design and Optimization for Three-Dimensional Integrated Circuits |
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X. Wu, P. Falkenstern (Penn State), K. Chakrabarty (Duke), and Y. Xie (Penn State) |
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9:00 - 9:30 |
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Using an X-Canceling MISR with Deterministic Observation for Increasing Output Compaction in Presence of Unknowns |
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R. Putman, R. Garg, and N.A. Touba (UT-Austin) |
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9:30 - 10:00 |
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S. Hwang, A. Guettaf, S. Ganta (Broadcom) |
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10:30–12:00PM |
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Delay Test |
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Chair: T.M. Mak (Intel) |
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10:30 – 11:00 |
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Scalable Identification of High Quality Path Delay Tests Under Launch-Off-Capture Scan Architecture |
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E. Flanigan, M. Goparaju, D. Jayaraman, S. Tragoudas (S. Illinois), M. Laisne, H. Cui, T. Petrov (Qualcomm) |
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11:00 – 11:30 |
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An Efficient Dynamic Compaction Approach for Path Delay Test |
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Z. Wang, D.M.H. Walker (Texas A&M) |
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11:30 – 12:00 |
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A Path-Oriented Timing-Aware Diagnosis Methodology of At-Speed Structural Tests |
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J. Wang, J. Zeng, M. Mateja (AMD) |
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1:30 - 3:30 PM |
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Fault Detection |
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Chair: R. Daasch (Portland State) |
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1:30 – 2:00 |
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On Detecting Scan Chain Internal Faults |
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F. Yang (U. Iowa), S. Chakravarty, N. Devta-Prasanna (LSI), S.M. Reddy (U. Iowa), I. Pomeranz (Purdue) |
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2:00 – 2:30 |
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S. Khatri, S. Ganesan (Texas A&M) |
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2:30 – 3:00 |
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Time-Multiplexed Online Checking: A Feasibility Study |
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M. Gao, H.-M. Chang, P. Lisherness, K.-T. Cheng (UCSB) |
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3:00 – 3:30 |
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A Fault-Tolerant Mechanism for Analog Systems |
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A. Namazi, S. Askari, M. Nourani (UT-Dallas) |
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4:00 - 6:00 PM |
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PANEL: Fast Clocks, Low Power, and Small Geometries: Big Problems for Test? |
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Moderator: Saghir Shaikh (Cadence) |
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Panelists: |
Tsvetomir Petrov (QualComm) |
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Al Crouch (ASSET InterTech) |
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Hank Walker (Texas A&M) |
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Rohit Kapur (Synopsys) |
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7:30 - 8:30 AM |
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CONTINENTAL BREAKFAST |
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8:30 - 10:00 AM |
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Test and Fault Tolerance |
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Chair: M. Nourani (UT-Dallas) |
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8:30 – 9:00 |
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Expanding Observation Window for Trace Buffer via Selective Data Capture |
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J.-S. Yang, N. Touba (UT-Austin) |
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9:00 - 9:30 |
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Study on Test Power Reduction for Scan-Based Hybrid BIST |
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M. Arai, A. Suto, K. Iwasaki (Tokyo Met. Univ.) |
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9:30 – 10:00 |
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C.-Y. Huang, T.-H. Ko, J.-L. Huang (NTU) |
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10:30-12:00 PM |
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Test Generation and Reliability |
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Chair: S. Khatri (Texas A&M) |
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10:30 – 11:00 |
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X. Lin (Mentor), S. Reddy (U. Iowa) |
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11:00 – 11:30 |
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Reliable Nanometer VLSI Systems using NMR Logic Gates |
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A. Namazi, M. Nourani (UT-Dallas) |
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11:30 – 12:00 |
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Reducing the Cost of Test – An Adaptive Test Solution |
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R. Turakhia, M. Ward (LSI), R. Daasch (Portland State) |
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